The present invention relates to the field of pulse width modulation ("PWM") and power converters. More specifically, one embodiment of the invention provides an improved apparatus for converting power at one DC ("direct current") voltage to power at another DC voltage ("DC/DC converter") or converting power at a DC voltage to power at an AC ("alternative current") voltage ("inverter").
FIG. 1 is a schematic diagram of a circuit 10 for generating an output voltage based on a duty cycle of a pulse width modulated signal. Such a circuit is widely used in motor drive and uninterruptible power supply ("UPS") applications as well as in DC/DC converters. Circuit 10 is shown comprising two transistors 12, 14 interposed in series between positive (V+) and negative (V-) voltage rails. The transistors 12, 14 connect at an intermediate node, designated here as node 16. A diode 17 is placed between node 16 and the V+ rail for flowing current from node 16 to the V+ rail when the voltage at node 16 exceeds the V+ rail voltage by more than a diode drop and a diode 18 is placed between node 16 and the V- rail for flowing current from the V- rail to node 16 when the voltage at node 16 falls more than a diode drop below the V- rail voltage. An inductor 19 is placed between node 16 and an output terminal V.sub.OUT to even out the flow of current throughout a duty cycle of a PWM input signal. In some cases, inductor 19 is part of the load itself. A motor is one example of an inductive load.
In operation, the gates of transistors 12, 14 are driven by a varying duty cycle PWM signal, V.sub.IN, and its complement, V.sub.IN#. Inductor 19 at the output acts as a low pass filter to recover the modulating signal. In motor drive and UPS applications, the modulating signal is usually a sine wave, while in DC/DC conversion applications, the modulating signal is a slowly varying DC voltage. Typically, the rail voltages are much larger than the drain-source voltage drops of transistors 12, 14, and therefore, circuit 10 efficiently transfers power from the rails to the output. A specific application might use V+=+300V and V-=-300V.
FIG. 2 shows an example of the input waveforms and node waveform as might occur when the instantaneous output voltage to be generated is V.sub.OUT =+200V. To achieve this output voltage, transistor 12 is turned on for 5/6 of a PWM cycle and transistor 14 is turned on for the remaining 1/6 of the PWM cycle. The current flowing through the transistors 12, 14 flows through inductor 19 to the output V.sub.OUT. As shown in FIG. 2, when transistor 12 is turned on at time t.sub.0, node 16 will be at nearly +300V and V.sub.OUT will be at +200V, giving a +100V drop across inductor 19 (the +200V is present at the output because of previous cycles not shown in FIG. 2). From time t.sub.0, the current through inductor 19 will increase at a rate of ((V+)-V.sub.OUT)/L, or +200V/L, and thus the current increase from t.sub.0 to t.sub.1, during which time transistor 12 is on, is [(V+)-V.sub.OUT)/L](t.sub.1 -t.sub.0).
At time t.sub.1, transistor 12 is turned off and transistor 14 is turned on. From t.sub.0 to t.sub.1, inductor 19 stored energy, E, equal to 1/2*LI.sup.2, where I is the inductor current at time t.sub.1. After transistor 14 is turned on, the voltage at node 16 is nearly -300V and V.sub.OUT is +200V. With the change in voltage across inductor 19, inductor 19 will lose current at the rate of ((V-)-V.sub.OUT)/L, or -500V/L. During this second interval (t.sub.1 to t.sub.2), the output current can be maintained from the energy the inductor accumulated in the first interval (t.sub.0 to t.sub.1).
In the steady state, the current in inductor 19 drops at time t.sub.2 to the same value it had at time t.sub.0 (and if V.sub.IN is periodic, the signals from t.sub.2 on are equivalent to those from t.sub.0 on). In both intervals, the direction of current through inductor 19 is the same. In the first interval, the current flows from the V+ rail through transistor 12, and then through inductor 19 to the output node V.sub.OUT. During the second interval, the current flows from the V- rail through transistor 14, or diode 18 depending on the type of transistor used, and then through inductor 19 to node V.sub.OUT. The current flows from the V- rail through inductor 19 because inductor 19 forces node 16 below V- to keep current flowing. If transistor 14 is a DMOS ("double diffused MOS") transistor, diode 18 is included as part of the transistor itself. If transistor 14 is an IGBT ("insulated gate bipolar transistor"), diode 18 is physically separate from transistor 14. In either case, current flows through diode 18 during the second interval.
It is well known that, during forward conduction, charge is stored in a diode and this charge has to be removed before the diode will turn off, resulting in a "reverse recovery time" which is nonzero. IGBT transistors also store charge during conduction that needs to be removed before the transistor will turn off, resulting in a nonzero turn-off time. However, for efficient operation of circuit 10, transistors 12, 14 and diode 18 must change conduction state in as short a time as possible to avoid loss of energy and stress on the components. Furthermore, the gate parasitic inductance is part of the gate-source path and that inductance must be low enough so that transistor 14 does not turn on at t.sub.2.
Referring to FIG. 2, when the signals V.sub.IN and V.sub.IN# switch at t.sub.1, transistor 12 does not turn off as fast as transistor 14 turns on, since the turn-on time for the transistors is shorter than the turn-off time. With such asymmetric switching times, both transistors will conduct temporarily between the on-switching of one transistor and the off-switching of the other transistor. This is very detrimental to the circuit's efficiency and the components involved. If both transistors 12 and 14 were on at the same time, a very high current would flow from the V+ rail to the V- rail, through the transistors 12, 14. The voltage across the transistors is 600V and the current is many times higher than the normal operating current of the transistors, creating a very high instantaneous power dissipation and resultant heating of the transistors.
The problem of having both transistors on at the same time can be avoided by skewing V.sub.IN and V.sub.IN# such that there is a "dead time" between when the gate of transistor 12 is driven low by V.sub.IN and the gate of transistor 14 is driven high by V.sub.IN#, and vice versa. Even with this problem solved, another similar problem occurs at t.sub.2, when transistor 14 is turned off and transistor 12 is turned on. During the second interval (from t.sub.1 to t.sub.2), diode 18 conducts current from the negative rail to inductor 19. At the end of the second interval, transistor 14 is turned off and, after the dead time, transistor 12 is turned on. Even though transistor 14 is off by the time transistor 12 turns on, diode 18 still conducts current from inductor 19, since node 16 is below the negative rail voltage due to the stored energy in inductor 19. When transistor 12 turns on, it will supply current to inductor 19 through node 16 and pull node 16 positive toward the V+ rail, in effect rerouting the current that was flowing to inductor 19 from the V- rail through diode 18. Eventually, the voltage at node 16 will rise and diode 18 will turn off. However, before diode 18 can turn off, it must lose its stored charge. Therefore, there is a small period where diode 18 is reverse biased but is still on. While the stored charge in diode 18 is being removed, a very high current will flow from the V+ rail through transistor 12 and diode 18 to the V- rail. This current flows across the full 600V and results in high power dissipation in transistor 12 and diode 18, causing excessive heating of these components and reducing circuit efficiency.
To limit this second problem, fast recovery diodes are used for diodes 17, 18. Even with fast recovery diodes, there is a nonzero recovery time during which transistor 12 must carry the sum of the inductor current and the reverse recovery current of diode 18. The reverse recovery current can be many times the inductor current, putting a high stress on transistor 12 and other components. Having transistor 12 turn on gradually, so that diode 18 can become reverse biased and lose its stored charge before transistor 12 turns completely on can reduce this problem. While this reduces the energy loss through diode 18 during diode reverse recovery, energy loss due to the simultaneous presence of high voltage and current across transistor 12 increases when a relatively slow switching period is used.
A further problem with circuit 10 is that transistor 12 imposes an unnecessarily high rate of voltage change (dV/dt) on transistor 14. Since transistor 14 must remain in the off state during the transition at time t.sub.2, transistor 14 must have a very low impedance gate drive circuit to be able to shunt the current injected into the gate of transistor 14 by its own gate-drain capacitance. At t.sub.2 (which is the same as t.sub.0 for a periodic V.sub.IN), the sharp increase in voltage at node 16 will cause a current to flow through the drain/gate capacitance (I=C * dV/dt) of transistor 14. With a nonzero impedance in the V.sub.IN# signal source, that current flow will cause the voltage at the gate of transistor 14 to rise (by I times the source impedance), and that increase in voltage will try to turn on transistor 14, as the signal source is connected across the gate and source of transistor 14.
This requirement complicates the gate drive circuit. If one chooses to reduce losses using the gradual turn-on approach described above, then the gate drive circuit must have a higher impedance when the transistor is to be turned on and a lower impedance when the transistor is to be turned off. This requires additional components, increasing cost and circuit board space. In many cases, the gate circuit parasitic inductance by itself is high enough that, combined with a nonzero impedance in a gate drive circuit, results in a transistor erroneously turning on due to the voltage increase at the gate from that parasitic inductance. To avoid this, a negative voltage might be applied between the gate and the source, but this requires an additional power supply, adding even more cost to the circuit.
FIG. 3 is a schematic of a circuit 30 that has been used to solve some, but not all, of the foregoing problems. Circuit 30 is similar to circuit 10 in FIG. 1, with an additional parallel diode/inductor circuit in series with diode 17 and a similar circuit in series with diode 18. As shown in FIG. 3, a diode 32 is in parallel with an inductor 36 and both are in series with diode 17, while a diode 34 is in parallel with an inductor 38 which are both in series with diode 18. Relative to inductor 19, inductors 36, 38 are of a much smaller inductance.
Minimizing the dead time and using two diodes in place of one with an inductor across one of the diodes reduces switching losses. At least one of diodes 17, 32, 18, 34 will not be conducting at any given time. At t.sub.2, diode 34 is not conducting. Instead of current flowing through diode 34, the output current flows through diode 18 and inductor 38. This allows diode 34 to be already in the off state when the next switching occurs. At t.sub.2, inductor 38 and diode 34 will allow the voltage at node 16 to rise, giving time for diode 18 to turn off without high current through transistor 12.
Circuit 30 does not solve all of the problems with these circuits, as it does not prevent excessive current flow along the transistor 12 to transistor 14 path when the dead time is not long enough to prevent both transistors from being on simultaneously. The problem with transistor 12 imposing a high dV/dt on transistor 14 is also not solved with circuit 30.
FIG. 4 is a schematic of a circuit 40 developed by the present inventor which prevents both types of "shoot-through" current (due to simultaneously on transistors and diode reverse recovery times), but at the expense of using capacitors and resistors. Circuit 40 is similar to circuit 10, but with the addition of a four-component circuit inserted in series between each of the transistors and their associated rails. An inductor 41 is in series between the V+ rail and the drain of transistor 12, while a diode 42 is in series with an RC circuit and the diode-RC combination is in parallel with inductor 41. The RC circuit comprises a capacitor 43 and a resistor 44 in parallel. A similar circuit is interposed between transistor 14 and the V- rail using inductor 46, diode 47, capacitor 48 and resistor 49. Any energy accumulated in inductor 41 (built up when transistor 12 is on and current is flowing from the V+ rail through transistor 12) is dissipated by resistor 44 when transistor 12 turns off and inductor 41 needs to keep current flowing. Likewise, energy accumulated in inductor 46 when transistor 14 is on is dissipated by resistor 49. This is undesirable because it causes circuit heating and loss of power transfer efficiency.
Yet another problem in the above-described circuits is that the fast recovery (freewheeling) diodes have a slow forward recovery. In other words, there is a delay between the time a forward bias has been applied to the diode and the time the diode begins to conduct. So long as there is a forward bias (i.e., node 16 is outside the rail voltages) and no diode has turned on, the voltage across one of the transistors will be in excess of 600V. In part, the delay in getting conduction through the diodes is due to the parasitic inductances in series with the diodes.
FIG. 5 is a schematic of circuit 10 with the circuit's parasitic inductances explicitly shown as inductors L1 to L8. These parasitic inductances are due, at least in part, to the nonzero lengths of the circuit interconnections. When circuit 10 is switching, voltage spikes develop across the inductors. Such spikes are particularly troublesome after the reverse recovery (shut off) of diode 18 at t.sub.2, when the current through diode 18 drops suddenly, thereby causing a negative voltage spike at node 16 and at the source of transistor 12 as parasitic inductances L5 and L8. L5 and L8 try to keep current flowing through themselves. L3 acts likewise and tries to pull the drain transistor 12 positive with respect to the V+ rail. That negative voltage spike at the source and the positive spike at the drain will increase the voltage across transistor 12. Because of this, a circuit 10 is usually designed with 600V transistors for 300V rail-to-rail voltage (or double the supply voltage) to handle the normal rail-to-rail voltage plus the excess voltage resulting from the voltage spikes. This was the disadvantage that slower, more expensive transistors must be used. A voltage spike will also appear across L6 and L7 if the dead time is not sufficient for commutating transistors 12 and 14, which also requires higher voltage transistors to withstand the spikes.
FIG. 6 is a schematic of an inverter circuit 60 that improves somewhat on the circuits described above. In circuit 60, the functions of transistors 12, 14, diodes 17, 18 and inductor 19 are as previously described. However, an inductor 62 is interposed in series between the source of transistor 12 and node 16, while an inductor 64 is interposed in series between node 16 and the drain of transistor 14. A diode pair 66 is connected to flow current from the drain of transistor 14 to the V+ rail should that drain rise above V+. A second diode pair 68 is connected to flow current from the V- rail to the source of transistor 12 should that source drop below V-. As with the circuits shown in FIGS. 1, 3 and 4, in normal operation, circuit 60 is cycled through two intervals. In the first interval, transistor 12 is turned on and in the second interval, transistor 14 is turned on. The relative lengths of the intervals (duty cycle) determine the output voltage.
During the first interval (the time period from time to t.sub.0 time t.sub.1 in the timing diagrams), current in circuit 60 flows from the V+ rail through transistor 12, inductor 62 and inductor 19 to the output V.sub.OUT. At t.sub.1, transistor 12 turns off and transistor 14 turns on. If transistor 12 does not turn off quickly enough before transistor 14 turns on, a small amount of current will build up in inductor 64 due to the conduction path through transistors 12, 14 and inductors 62, 64. After transistor 12 stops conducting, node 16 and node 70 (the source of transistor 12) will drop in voltage due to the energy stored in inductors 62 and 19. The drop in voltage at node 70 will cause the voltage at node 72 (the drain of transistor 14) to rise due to the energy stored in inductor 64, which generates current through transistor 14. The result is that the load current (the current through inductor 19) will be carried and shared by: 1) inductor 62 and diode pair 68, 2) inductor 64 and transistor 14, and 3) diode 18. This allows most of the energy stored in the inductors 62, 64 to be recovered.
At t.sub.2, transistor 14 is turned off and transistor 12 is turned on. When that happens, the voltage at node 16 will drop until it is below V- and diode 18 turns on to carry the load current. With suitable component values, inductor 62 will have essentially discharged by this time, and since diode 18 does not have enough of a voltage across it to turn on diode pair 68, diode pair 68 is off.
As transistor 12 turns on, current will start to build up in inductor 62, increasing until it equals the load current flowing through inductor 19. The time it takes for the current to increase to that point can be designed into circuit 60 by selecting the appropriate value for inductor 62. The gate signal V.sub.IN to transistor 12 can be switched at the same time as the gate signal V.sub.IN# to transistor 14, because inductors 62 and 64 limit the current that can pass through transistors 12 and 14 from rail to rail to a value much less than the normal operating current the transistors must support.
Because of this, the amount of time where both voltage and current are simultaneously present on transistor 12 is reduced, thus reducing power dissipation during turn-on. After the current in inductor 62 equals the load current, the current will stop increasing, causing the voltage across inductor 62 to drop, thereby raising the voltage of node 16. The voltage at node 16 will rise until diode 18 is reverse biased. Before that happens, however, diode 18 is on and has stored charge. As the voltage increases at node 16, diode 18 will respond with its reverse recovery current flowing from node 16 to the V- rail. This reverse recovery current is provided by inductor 62. The rate of increase of current in inductor 62 is limited to [(V+)-(V-)]/L62 (the voltage drops across transistor 12 and diode 18 are much less than the rail-to-rail voltage, so those voltage drops are left out of this equation for simplicity) where L62 is the inductance of inductor 62. Because of this limit, the rate at which sufficient current can be obtained to supply the reverse recovery current of diode 18 is limited. Limiting the reverse recovery current is important because its value can be from 10 to 100 times the normal operating current. The reverse recovery current is limited without slowing the transistors' switching speed, but circuit 60 still has additional disadvantages as explained below.
Once all the stored charge is removed from diode 18, it turns off and the voltage at node 16 is free to increase. As the load current flows through inductor 62, the voltage at node 16 will increase as the excess energy of inductor 62 is discharged and the voltage drop across inductor 62 decreases. Eventually, the voltage across inductor 62 will decrease so far that node 16 is more positive than node 70. This additional voltage (the voltage increase at node 16) allows the recovery of a small part of the excess stored energy of inductor 62, but the rest of the excess stored energy turns into heat dissipated in transistor 12 and diode 17.
Inductor 62 retains a high current until its stored energy is discharged. As mentioned above, the voltage across inductor 62 when node 16 goes positive is the sum of the on-state voltages of transistor 12 and diode 17. This amounts to a few volts. At that voltage, the discharge of inductor 62 takes a significant portion of the pulse width, and for the duration, the current remains relatively high through transistor 12 and diode 17. This detracts from the effectiveness of this technique to reduce stress on the components and to reduce power dissipation. The additional voltage amounts to the forward drop on diode 17, which is below 1V.
A specific example illustrates the effect of the circuit's operation. Assume a load current in inductor 19 of 10 A (amps). With that load current, the peak reverse recovery current in diode 18 might be about 30 A (limited by inductor 62). That 30 A current will continue to flow through inductor 62 even after the voltage at node 16 rises above V+, but diode 17 will limit the voltage rise at node 16 to about 1V above V+. At that point, the 30 A through diode 18 is split with 10 A flowing through inductor 19 and the other 20 A flowing through diode 17. The 30 A flows through transistor 12, causing some excess voltage drop across transistor 12. The current in inductor 62 has to drop to 10 A (the load current) by discharging its excess energy. The energy directed to the load is proportional to the voltage rise of node 16 above V+ and the load current. The loss is proportional to the excess voltage drop across transistor 12 multiplied by the current through transistor 12 (30 A) and the forward voltage of diode 17 and the current through it (20 A). As a result, inductor 62 (and inductor 64) reduces the peak current during reverse recovery, allowing for lower powered circuit devices, but most of the stored energy is dissipated in transistor 12 and diode 17.
Diode pairs 66, 68 are selected for optimum forward recovery to prevent any excess voltage in circuit 60 by effectively clamping the voltage across the transistors 12, 14 to the V+ and V- rails. Since the inductors 62, 64 prevent the build-up of high currents through the transistors, the components of circuit 60 are exposed to minimal stress irrespective of whether or not a dead time is used. By recovering part of the stored energy from inductors 62, 64 and switching transistors 12, 14 quickly, circuit 60 improves the efficiency of circuit 60 somewhat, but still dissipates excessive stored power.
While the transistors 12, 14 switch at maximum speed, the change in voltage (dV/dt) imposed on the transistor that is in the off state is lower than in circuit 10, because of the inductors used in series with the transistors. Also, the inductors 62, 64 have the effect of forming a low pass filter with their corresponding transistor's internal capacitance. For example, at t.sub.2 the voltage at node 16 is rising and the voltage at node 72 will rise slower due to inductor 64 and the collector capacitance of transistor 14.
FIGS. 7(a)-(e) form a timing diagram showing the voltages at various nodes in the circuit of FIG. 6 over a little more than one cycle of V.sub.IN. The vertical scales are not necessarily the same from line to line and the time scale is not necessarily to scale, so as to emphasize the relevant features of the voltages. FIG. 7(a) shows the signal applied to V.sub.IN, while FIG. 7(b) shows the signal applied to V.sub.IN#. It should be noted that V.sub.IN rises when V.sub.IN# falls and vice versa (no overlap is needed).
FIGS. 7(c)-(d) show the voltages, V.sub.70 and V.sub.72, at nodes 70 and 72, respectively. At t.sub.0, when transistor 12 turns off and transistor 14 turns on, V.sub.70 falls to below V- as inductor 62 attempts to maintain its current flow just before the transition. V.sub.70 falls until diode pair 68 turns on and shunts the inductors' stored energy through the path provided by diode pair 68, inductor 62, and inductor 19. V.sub.72 drops to follow node 16 as inductor 64 seeks to maintain its prior state of no current flow. Once inductor 62 is de-energized, V.sub.70 rises to just below V-. V.sub.70 is pulled below V- by the combined action of inductor 62 having no stored energy and zero voltage across it and inductor 19 trying to maintain its current flow. As shown in FIG. 7(c), the fall of V.sub.70 stops when diode pair 68 turns on.
At t.sub.1, when transistor 14 turns off and transistor 12 turns on, V.sub.70 rises to just below V+ since transistor 12 is on. V.sub.16 and V.sub.72 rise above V+ as inductor 62 attempts to maintain the current flow it built up just before t.sub.1 from the reverse recovery of diode 18, until diode pair 66 and diode 17 turn on and shunt the inductor's (62) stored energy through transistor 12, inductor 62, and diode 17. V.sub.70 rises as transistor 12 turns on. Once inductor 62 is de-energized, V.sub.70 and V.sub.72 settle to just below V+.
FIG. 7(e) shows the voltage V.sub.16 at node 16. At t.sub.0, transistor 12 turns on and transistor 14 turns off. Initially, the voltage on node 16 does not change because diode 18 is able to conduct current for a short time, t.sub.e, as diode 18 releases its reverse recovery charge. Once diode 18 turns off, V.sub.16 rises to (V+)-V.sub.e2, where V.sub.e2 is the drop across transistor 12. Actually, V.sub.16 initially rises above V+, pulled by the energy stored in inductor 62, until inductor 62 discharges. From this point in time until the next switch at t.sub.1, there is no voltage across inductors 62 and 64. The current in inductor 62 decays at a rate of (V12+V17)/L62, as shown in FIG. 7(e), where V12 is the drain-source voltage across transistor 12, V17 is the voltage drop across diode 17 and L62 is the inductance of inductor 62.
At t.sub.1, transistor 12 turns off and transistor 14 turns on. In response, V.sub.16 drops to just above V- due to the energy stored in inductor 62 while transistor 12 was conducting. Inductor 62 discharges this energy by pulling node 70 negative until diode pair 68 turns on so current can be conducted through diode pair 68, inductor 62 and inductor 19. The energy in inductor 62 will hold node 16 above V- until inductor 62 discharges. In this way, part of the energy stored in inductor 62 will be transferred to the load, but most of the stored energy is lost to heat. The same is true for inductor 64 in the opposite phase. Once inductor 62 discharges, V.sub.16 settles to (V-)-V.sub.e1, where V.sub.e1 is the forward voltage on diode 18.